The present invention relates to a semiconductor device and a fabricating method thereof, and more particularly, to a submicron channel MOSFET and a fabricating method thereof.
In general, the length of a channel must be shortened to reduce the size of a MOSFET. Hence, various approaches have been conducted to develop MOSFETs having a submicron channel. However, when a MOSFET becomes a submicron channel, that is, a short channel, the unit devices (unit MOSFETs) of a highly-integrated circuit have different distributions of impurities in a channel region, leading to a problem in which the unit devices have different threshold voltages. Also, the junction depth of a source/drain region must be thin while a MOSFET becomes a short channel.
The problem in which the unit devices of a highly-integrated circuit have different threshold voltages has been solved to some extent by adopting a double-sided gate or a back plane gate. This problem would not be solved completely as far as there are impurities in a channel region, since the difference in threshold voltage between unit devices is caused by the impurities in the channel region.
The problem in that a thin source/drain region must be formed has been solved by using a thin electrically-formed inversion layer as a source/drain region, since a thin source/drain region cannot be not formed when ion implantation is used.
FIG. 1 is a cross-sectional view of a conventional submicron channel MOSFET. To be more specific, a thin oxide film 107a and a thick oxide film 107b are formed on a P-type substrate 101 on which a source region 103 and a drain region 105 have been formed. A main gate 109 is formed on the thin oxide film 107a, and sub-gates 111 are formed on the thick oxide film 107b. In the conventional submicron channel MOSFET using the main gate 109 and the sub-gates 111 as described above, inversion layers 113 are formed under the sub-gates 111 by applying voltage to the main gate 109 and the sub-gates 111, and the formed inversion layers 113 are used as a thin source/drain.
However, the conventional submicron channel MOSFET of FIG. 1 has a problem associated with a process, in that a special pad must be made to apply voltage to the sub-gates 111.
Also, in the conventional extra-small channel MOSFET of FIG. 1, a high voltage must be applied to the sub-gates to form inversion layers 113, that is, the thin source and drain.
An object of the present invention is to provide a submicron channel metal oxide semiconductor field effect transistor (MOSFET) in which a thin source/drain region can be formed under sub-gates without formation of a special pad, and by which non-uniformity of threshold voltage between the unit devices of a highly-integrated circuit can be solved.
Another object of the present invention is to provide a method of fabricating the submicron channel MOSFET.
The first object of the present invention is achieved by a submicron channel metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention, wherein N+ source/drain regions are formed near the surface of a Pxe2x88x92silicon substrate, having a channel therebetween, a gate dielectric film is formed on the channel, a main gate is formed on the gate dielectric film on the channel, and sub-gates having a smaller work function than the main gate are formed on the gate dielectric film and on the sidewalls of the main gate covered with a dielectric film.
The main gate can be formed of P+ polycrystalline silicon, and the sub-gates can be formed of N+ polycrystalline silicon. The main gate can be formed of SiGe or a metal having a work function that is smaller than that of P+ polycrystalline silicon and greater than that of N+ polycrystalline silicon, and the sub-gates can be formed of N+ polycrystalline silicon. The sub-gates can be formed of a conductive material having a work function that is equal to or smaller than that of N+ polycrystalline silicon, and the main gate can be formed of P+ polycrystalline silicon.
In the submicron channel MOSFET of the present invention as described above, there is a difference in work function between a main gate and sub-gates, and the main gate is formed of P+ polycrystalline silicon on a Pxe2x88x92 substrate, so that the concentration of impurities for controlling a threshold voltage implanted into a channel region under the main gate can be reduced as much as possible. This leads to a minimization of the difference in threshold voltage between the unit devices of a highly-integrated circuit due to the non-uniformity of the impurities for controlling a threshold voltage.
Also, in the submicron channel MOSFET of the present invention, thin inversion layers used as source/drain regions under the sub-gates are formed because of the difference in work function between the main gate and the sub-gates. Furthermore, in the submicron channel MOSFET of the present invention, the sub-gates are formed of N+ polycrystalline silicon, and a Pxe2x88x92 silicon substrate having a low concentration is used, so that thin inversion layers are formed under the sub-gates. Hence, voltage does not need to be applied to the sub-gates, so that a special metal pad does not need to be formed.
The submicron channel MOSFET described above denotes an N-MOSFET. However, the contents described above can be applied to P-MOSFETs.
In a submicron channel MOSFET according to another embodiment of the present invention to achieve the first object of the present invention, P+ source/drain regions are formed near the surface of an Nxe2x88x92 silicon substrate, having a channel therebetween. A gate dielectric film is formed on the channel, and a main gate is formed on the gate dielectric film on the channel. Sub-gates having a greater work function than the main gate are formed on the gate dielectric film and on the sidewalls of the main gate covered with a dielectric film. Here, inversion layers formed under the sub-gates act as thin source/drain regions.
The main gate can be formed of N+ polycrystalline silicon, and the sub-gates can be formed of P+ polycrystalline silicon. The main gate can be formed of SiGe or a metal having a work function that is smaller than that of P+ polycrystalline silicon and greater than that of N+ polycrystalline silicon, and the sub-gates can be formed of P+ polycrystalline silicon. The sub-gates can be formed of a conductive material having a work function that is equal to or smaller than that of P+ polycrystalline silicon, and the main gate can be formed of N+ polycrystalline silicon.
The second object of the present invention is achieved by a method of fabricating a submicron channel MOSFET, wherein a gate dielectric film is formed on a Pxe2x88x92 silicon substrate, a main gate is formed on the gate dielectric film, a dielectric film is formed to surround the main gate, sub-gates having a smaller work function than the main gate are formed on the dielectric film on the sidewalls of the main gate, and N+ source/drain regions are formed by implanting N-type impurities into the entire surface of the Pxe2x88x92 silicon substrate on which the main gate, the dielectric film and the sub-gates are formed. Here, inversion layers formed under the sub-gates act as thin source/drain regions.
The main gate can be formed of P+ polycrystalline silicon, and the sub-gates can be formed of N+ polycrystalline silicon. After the sub-gates are formed, a P0 region can be formed near the N+ source/drain regions under the sub-gates by tilt ion implanting P-type impurities toward the sidewalls of the sub-gates. Before the gate dielectric film is formed, a P0 region having a higher doping concentration than the Pxe2x88x92 silicon substrate can be formed within the Pxe2x88x92 silicon substrate.
The second object of the present invention is also achieved by a method of fabricating a submicron channel MOSFET, wherein a gate dielectric film is formed on an Nxe2x88x92 silicon substrate, a main gate is formed on the gate dielectric film, a dielectric film is formed to surround the main gate, sub-gates having a greater work function than the main gate are formed on the dielectric film on the sidewalls of the main gate, and P+ source/drain regions are formed by implanting P-type impurities into the entire surface of the Nxe2x88x92 silicon substrate on which the main gate, the dielectric film and the sub-gates are formed. Here, inversion layers formed under the sub-gates act as thin source/drain regions.
Before the gate dielectric film is formed, an N0 region having a higher doping concentration than the Nxe2x88x92 silicon substrate can be formed within the Nxe2x88x92 silicon substrate. The main gate can be formed of N+ polycrystalline silicon, and the sub-gates can be formed of P+ polycrystalline silicon. After the sub-gates are formed, an N0 region can be formed near the P+ source/drain regions under the sub-gates by tilt ion implanting N-type impurities toward the sidewalls of the sub-gates.